Historically
In video systems, the information displayed is segmented into discrete elements referred to as "pixels", the number of pixels per unit area determines the available resolution. Each of these pixels, for a simple black and white system, can be defined in terms of one bit of data; whereas, a more complex system utilizing pixels having differing colors and intensity levels requires significantly more bits of data. To display the pixel information stored in memory, data is read from memory and then organized in an interim storage medium having a serial format. As each horizontal line in the display is scanned, the pixel data is serially output and converted to video information. For example, the stored data for each black and white pixel correspond to a predetermined position in the scan line and determines the video output for either "white" level or a "black" level.
Two of the primary features of a pixel memory storage unit, referred to as a Video Random Access Memory or VRAM for short, are the number of pixels required per scan line and the scanning rate. This determines how the pixel information is mapped into the memory and the rate at which the stored pixel information must be accessed and serially output. Typically, video memories are "pixel mapped" such that one row of memory elements or portion thereof directly corresponds to the pixel information of a given scan line or portion thereof. For example, in a black and white system having 256 pixels per scan line, a memory having 256 memory elements per row would be utilized. The information in the row is accessed and stored in a serial shift register for serial output therefrom during a given scan line, thereby requiring only one memory access per scan line. While data is being output from the serial shift register to the display, data is being accessed from the memory for updating of display data. This data is transferred to the shift register during the retrace period between adjacent scan lines. Therefore, the number of rows and columns of memory elements is determined by the number bits of information per pixel and the number of scan lines in the display.
In applications utilizing pixel mapped video memories, a large number of individual memories are arranged in arrays such that a single access operation outputs a predetermined pixel pattern. This allows a large number of pixels and/or bits per pixel to be output during a single access time, thereby reducing the time required to access a given set of information. This array configuration may require the shift registers associated with individual memories to be either cascaded or arranged in parallel.
To facilitate the use of multiple pixel mapped video memories, it is desirable to incorporate more than one memory on a single semiconductor chip. To provide a viable device from both an economical and a marketing standpoint, each of the integrated memories must maintain some degree of independent operation relative to the other memories on the same chip and yet share as many control functions as possible. This is necessary to reduce the number of integrated circuit pins required to interface between the peripheral circuitry and the chip itself, and also to reduce the circuit density. When multiple pixel mapped video memories are integrated onto a single semiconductor chip, it is desirable to have independent access to the serial inputs and outputs of each of the memories. Additionally, it is desired to have independent control of the random read/write control functions. However, if both independent access and control are integrated together, the architecture would result in an impractical multi-pin package. Additionally, the control circuitry required to provide the various independent functions would increase the density of the chip circuitry. Therefore, there is a need for independent access and control circuitry that utilizes a small portion of the chip.
FIG. 1 is a suitable representative illustration of the applicants overall functional block diagram teaching how a typical VRAM may work, and can be arranged. A VRAM often includes the following elements: The VRAM 10 has inputs and I/O lines and several inputs associated with a timing generator and control logic 84. The VRAMs pixel or bit memory is contained in a DRAM array 12, having four arrays each represented by 12.times.1, 12.times.2, 12.times.3, and 12.times.4. For the remainder of the description of FIG. 1, the drawing will not show the multiple circuits needed for arrays 12.times.2, 12.times.3 and 12.times.4. Each array is associated with a sense amplifier 15.times.1 through 15.times.4, and a single column decoder 14 which in turn is coupled to a column address latch/buffer 17. Additionally, the arrays 12 are responsive to transfer gates 16. There are two banks of transfer gates associated with each array, having the following numbering arrangement: 16.times.1a and 16.times.1b (indicating the first array on the left "a" and on the right "b"), 16.times.2a and 16.times.2b and so forth. It is noted that the text will use lower case lettering, while the figures use upper case lettering for the elements. Each left bank of transfer gates is associated with a lower SAM (sometimes known as a serial access memory, or a static addressable memory) 18.times.1a, 18.times.2a etc. Similarly, each right sided transfer gate bank is coupled to an upper SAM 18.times.1b, 18.times.2b, etc. All of the SAMs are directed by a SAM location decoder 20. Decoder 20 is coupled to a SAM output and input buffers 64 for a VRAM I/O, and coupled to a SAM address counter 56. Counter 56 is coupled to a SAM address latch/buffer 58 where both are associated with a split SAM status and control circuit 60, and a pass control logic circuit 62. One way the DRAM memory 12 is coupled to outside inputs is via row address latch/buffer 50 and row decoder 52. Refresh counter 54 is coupled to row address latch/buffer 50. Column latch 17 is coupled to a column mask circuit 66. DRAM input buffers 68 is coupled to the output of column mask 66. Decoder 14 is coupled to a DRAM output buffer 80 and to a MASK/write control logic circuit 74. Circuit 74 is coupled to DRAM input buffers 68 via color register 72, and mux 70. Mux 70 is also receiving signals from the column mask 66 which are also coupled to circuit 74. There is a block write control logic feeding into the register 72, mux 70 and column mask. Control logic circuit 74 also receives signals from a mask data register which is responsive to a masked write control logic 78, column mask 66 and DRAM input buffers 68.
Generally, where applicable, the figure numbering elements will be described without reference to other arrays since all arrays are similarly configured, and thus are similarly numbered.
FIG. 2 is a more detailed illustration of a related art DRAM memory array and associated circuitry, which in addition to the elements discussed in FIG. 1, further comprises the following new elements in reference to the first of the represented two memory blocks, labeled 12.times.1.
A P-channel transistor 30 generates a PSA (P-sense amplifier) strobe signal in response to a PLAT (P latch) signal 32. The PSA strobe signal strobes the P-sense amplifier. An N-channel transistor 28 generates an NSA (N-sense amplifier) strobe signal in response to an NLAT (N latch) signal 34. The NSA strobe signal strobes the N-sense amplifier. All PSAs (P-sense amplifiers) in the array respond to the PSA (P-sense amplifier) strobe signal, and all NSAs (N-sense amplifiers) in the array respond to the NSA (N-sense amplifier) strobe signal.